Nanometer Frequency Synthesis Beyond the Phase-locked Loop

by Xiu, Liming

Edition: 1st

ISBN13: 9781118162637

ISBN10: 1118162633

Format: Hardcover

Pub. Date: 2012-08-14

Publisher(s): Wiley-IEEE Press

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Summary

This text presents a latest technology in frequency synthesis. The technology includes three key components: Time-Average-Frequency, Flying-Adder architecture, and Digital-to-Frequency converter. The coverage presents the case, through real application examples, that this Flying-Adder technology creates a new frontier for modern IC design. In so doing, it also discusses the weaknesses of current frequency synthesis techniques in dealing with certain problems in modern IC design. The result is a complete picture of this technology for professional design engineers, researchers, and advanced students.

Author Biography

Liming Xiu is Chief Clock Architect at the Novatek Microelectronics Corporation and formerly a senior member of the technical staff at Texas Instruments Inc. Xiu served as vice president of the IEEE Circuits and System Society during 2009-2010. He has written numerous journal and conference papers, holds a number of patents, and is the author of VLSI Circuit Design Methodology Demystified from Wiley-IEEE Press.

Preface	p. xi
Clock Signal in Electronic Systems	p. 1
The Significance of Clock Signal	p. 1
Clock Signal	p. 1
The Aim of This Book	p. 3
The Characteristics of Clock Signal	p. 5
Jitter and Phase Noise	p. 5
Clock Phase	p. 13
Clock Skew	p. 15
Clock Signal Driving Digital System	p. 18
Clock Signal as a Trigger	p. 18
Timing-Closure Design Constraint: The Safeguard for Reliable Operation	p. 18
Clock Jitter and Design Constraint	p. 21
Clock Skew and Design Constraint	p. 21
Clock Signal Driving Sampling System	p. 24
Clock Signal as a Switch	p. 24
Clock Signal and Analog-to-Digital Converter	p. 25
Clock Signal and Digital-to-Analog Converter	p. 28
Extracting Clock Signal From Data: Clock Data Recovery	p. 30
Clock Usage in System-on-Chip	p. 32
Two Fields: Clock Generation and Clock Distribution	p. 33
Bibliography	p. 34
Clock Generation: Existing Frequency Synthesis Techniques	p. 37
Direct Analog Frequency Synthesis	p. 38
Direct Digital Frequency Synthesis	p. 39
Indirect Method (Phase-Locked Loop Based)	p. 41
Brief History	p. 41
The Basic Structure of the Phase-Locked Loop (PLL)	p. 42
An Example of Third-Order Type-II Charge Pump PLL	p. 45
Major PLL Architectures	p. 47
The Shared Goal: All Cycles Have Same Length-in-Time	p. 51
Bibliography	p. 51
Time-Average-Frequency	p. 53
The Scale of Level and the Scale of Time	p. 53
What Is Frequency?	p. 54
How Is Frequency Implemented In Circuit Design?	p. 55
How Is Frequency Used in Electronic System?	p. 55
"Instantaneous Frequency" and "Instantaneous Period"	p. 55
Reinvestigating the Frequency Concept: the Birth of Time-Average-Frequency	p. 56
Time-Average-Frequency in Circuit Implementation	p. 59
Average Frequency, Time-Average-Frequency, and Fundamental Frequency	p. 61
The Need of a Theory	p. 62
The Summary: Why Do We Need Time-Average-Frequency?	p. 63
Bibliography	p. 63
Flying-Adder Direct Period Synthesis Architecture	p. 65
The Working Principle	p. 65
The First Structure	p. 65
One Step Forward	p. 67
The Major Challenges in the Flying-Adder Circuit	p. 68
The Glitch Problem	p. 68
The Speed of Accumulator	p. 70
The Generation of the K Inputs	p. 70
The Circuit of Proof of Concept	p. 74
Using Two Paths to Solve the Glitch Problem	p. 74
Synchronize the Two Paths	p. 75
Pipeline for Adder Speed	p. 76
The Working Circuitry	p. 77
The Proof of Glitch-Free	p. 78
The Order of the Input Signals	p. 81
The Analysis of Circuit Speed	p. 81
The Analysis of Power Consumption	p. 82
The Behavioral Simulation	p. 82
The Extension to Multipaths	p. 85
Frequency Transfer Function, Frequency Range, Frequency Resolution, and Frequency Switching Speed	p. 87
The Technique of Post Divider Fractional Bits Recovery	p. 88
Post Divider Fractional Bits Recovery (PDFR)	p. 88
PDFR for Virtually Boosting the Number of Inputs K	p. 89
The Effective Fraction after Post Divider	p. 90
Flying-Adder PLL: FAPLL	p. 90
Flying-Adder Fractional Divider	p. 91
Integer-Flying-Adder Architecture	p. 92
Integer-Only FAPLL: How Close Can It Reach an Integer?	p. 92
Incorporating Flying-Adder Fractional Divider Inside Integer-N PLL	p. 94
Integer-Flying-Adder Architecture	p. 95
The Algorithm to Search Optimum Parameters	p. 98
The Construction of the Accumulator	p. 99
The Construction of the High Speed Multiplex	p. 104
Non-2's Power Flying-Adder Circuit	p. 107
Expanding VCO Frequency Range in Nanometer CMOS Processes	p. 109
Multiple Flying-Adder Synthesizers	p. 110
Flying-Adder Implementation Styles	p. 111
Simulation Approaches	p. 112
The Impact of Input Mismatch on Output Jitter	p. 113
The Cause of Mismatch and Its Characteristics	p. 113
The Mismatch Modeling	p. 116
The Mismatch and the Frequency Control Word	p. 117
The Mismatch's Impact on Output Period	p. 118
The Mismatch's Impact on Output Spectrum	p. 123
Summary on Mismatch's Impact	p. 125
Flying-Adder Circuit as Digital Controlled Oscillator	p. 127
Flying-Adder Terminology	p. 128
Flying-Adder Synthesizer and Time-Average-Frequency: The Experimental Evidence	p. 129
The FAPLL Structure	p. 129
Jitter Performance	p. 132
Frequency Generation Capability	p. 133
Frequency Resolution	p. 133
Frequency Spectrum	p. 133
Instantaneous Switching Demonstration	p. 137
Time-Average-Frequency Demonstration	p. 137
PDFR Demonstration	p. 144
XIU-Accumulator Evaluation	p. 144
Input Mismatch Observation	p. 146
The Flying-Adder Fractional Divider Used Inside PLL	p. 149
The Integer-Flying-Adder PLL	p. 151
Time-Average-Frequency and Setup Constraint: Revisit	p. 154
Sense the Frequency Difference: (The Time-Average-Frequency Way	p. 156
Flying-Adder and Direct Digital Synthesis (DDS): The Difference	p. 157
Flying-Adder for Phase (Delay) Synthesis	p. 158
Flying-Adder for Duty Cycle Control	p. 162
Flying-Adder Synthesizer in Reducing the Number of PLLs in SoC	p. 163
Bibliography	p. 164
Digital-To-Frequency Converter	p. 167
Two Ways of Representing Information	p. 167
The Converters for Transforming Information	p. 168
The Two Cornerstones of the Digital-to-Frequency Converter	p. 170
The Theoretical Foundation of Flying-Adder Digital-to-Frequency Converter	p. 172
Flying-Adder DFC Mathematical Model and Its State Variables	p. 173
Flying-Adder DFC as a Finite State Machine (FSM)	p. 174
The Periodicity in Discrete Time Domain	p. 175
The Periodicity in Continuous Time Domain	p. 176
The Time-Average-Frequency	p. 184
Pulse and Cycle in Time-Average-Frequency Signal	p. 185
Timing Irregularity in the Time-Average-Frequency Signal	p. 186
The Sample and Hold Method for Modeling DFC Output	p. 188
Frequency Spectrum of DFC Output	p. 190
Amplitude of the Time-Average-Frequency	p. 191
Relates the Mathematic Model with Real Circuit	p. 193
Convert the Spurious Energy to Noise Energy	p. 193
Move Spurs Around	p. 198
Spread the Energy	p. 201
Performance Merits	p. 205
Bibliography	p. 208
The New Frontier in Electronic System Design	p. 211
The Clocking Challenges in Reality	p. 211
The Environment	p. 211
Clock Signal for Computation	p. 212
Clock Signal for Synchronization	p. 213
IP Reference, Driving ADC/DAC, Frequency Conversion	p. 215
Frequency Multiplier versus Frequency Generator	p. 216
Flying-Adder and Its Three Major Application Areas	p. 216
Flying-Adder for On-chip Frequency Generation	p. 218
Flying-Adder as Adaptive Clock Generator	p. 222
Flying-Adder as On-chip VCXO	p. 230
Flying-Adder for Frame Rate Synchronization and Display Monitor Accommodation	p. 237
Flying-Adder for Frequency Synchronization in Digital Communication: A Preview	p. 240
Flying-Adder for Clock Data Recovery	p. 242
Flying-Adder DLL for Deskew	p. 255
Flying-Adder for Digital Frequency-Locked Loop (Flying-Adder DFLL)	p. 256
Flying-Adder for Digital Phase-Locked Loop (Flying-Adder DPLL)	p. 262
Flying-Adder Technology for Dynamic Frequency Scaling	p. 262
Flying-Adder as 1-bit DDFS	p. 264
Flying-Adder for Spread Spectrum Clocking	p. 265
Flying-Adder for Driving Sampling System	p. 268
Flying-Adder for Non-uniform Sampling	p. 271
Flying-Adder as Digital FSK Modulator	p. 273
Flying-Adder for PWM/PFW DC-DC Power Conversion	p. 274
Integrate Clocking Chips into Processing Chips	p. 275
Bibliography	p. 276
Looking into Future: The Era of "Time"	p. 279
The Four Fundamental Technologies in Modern Chip Design	p. 279
"Time"-Based Analog Processing	p. 281
"Time" and Frequency: Encoding Messages Through Modulation	p. 283
Manipulate "Time": The Tools	p. 283
It Is Time to Use "Time"	p. 284
But, Does This Make Sense?	p. 284
And, Is It Worth It?	p. 285
Will It Replace Level?	p. 285
Finally, Is It Ready?	p. 285
Appendices	p. 287
The VHDL Code for Flying-Adder Synthesizer	p. 287
How Close Can It Reach an Integer?	p. 296
The Seed and Set in Integer-Flying-Adder PLL	p. 299
The Number of Carries From an XIU-Accumulator	p. 302
The Flying-Adder State Machine Model (perl)	p. 303
The Flying-Adder Waveform Generator (perl)	p. 307
The Flying-Adder Waveform Generator with Triangular Modulation (perl)	p. 310
The Flying-Adder Waveform Generator with Random Modulation (perl)	p. 314
The FA-DCXO Tangent Line and Linearity Measurement	p. 318
Index	p. 321
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