This book is written for an advanced level course in Digital VLSI Systems Design using Verilog and is meant for undergraduates, graduates and research scholars of Electrical, Electronics, Embedded Systems, Computer Engineering and interdisciplinary departments such as Bio Medical, Mechanical, Information Technology, Physics, etc. It serves as a reference design manual for practicing engineers and researchers as well. Diligent freelance readers and consultants may also start using this book with ease. The book presents new material and theory as well as synthesis of recent work with complete Project Designs using industry standard CAD tools and FPGA boards, enabling the serious readers to design VLSI Systems on their own. The reader is taken step by step through the design right from implementing a single digital gate to a massive design consuming well over 100,000 gates. The Verilog codes developed for these designs are universal and can work on any FPGA or ASIC and are technology independent. The book presents the development of novel algorithms and architectures for optimum realization of high tech. products. All the design codes developed in this book are Register Transfer Level (RTL) compliant and can be readily used or amended to suit new projects.

Dr. S. Ramachandran is a project officer in the Electrical Engineering Department at the Indian Institute of Technology, Madras. He has a wide industrial and teaching experience, having worked both in India and USA, designing systems and teaching/guiding students based on FPGAs and Microprocessors. His research interests include developing algorithms, architectures and implementations on FPGAs/ASICs for Video Processing, DSP applications, reconfigurable computing, open loop control systems, etc. He is the recipient of the Best Design Award at VLSI Design 2000, International Conference held at Calcutta, India. He has a number of papers in International Journals and Conferences. He has completed a video course on Digital VLSI System Design along with Prof. S. Srinivasan.