Digital Systems Engineering,9780521592925

Digital Systems Engineering

by
ISBN13: 9780521592925
ISBN10: 0521592925
Format: Hardcover
Pub. Date: 1998-06-28
Publisher(s): Cambridge University Press
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Summary

What makes some computers slow? Why do some digital systems operate reliably for years while others fail mysteriously every few hours? How can some systems dissipate kilowatts while others operate off batteries? These questions of speed, reliability, and power are all determined by the system-level electrical design of a digital system. Digital Systems Engineering presents a comprehensive treatment of these topics. It combines a rigorous development of the fundamental principles in each area with real world examples of circuits and methods. The book not only serves as an undergraduate textbook, filling the gap between circuit design and logic design, but can also help practising digital designers keep pace with the speed and power of modern integrated circuits. The techniques described in this book, once used only in supercomputers, are now essential to the correct and efficient operation of any type of digital system.

Table of Contents

Preface xxi(4)
Acknowledgment xxv
1 INTRODUCTION TO DIGITAL SYSTEMS ENGINEERING
1(24)
1.1 Why Study Digital Systems Engineering?
2(2)
1.2 An Engineering View of a Digital System
4(8)
1.2.1 Feeds and Speeds
5(1)
1.2.2 Signaling Conventions
6(1)
Signaling Speed
7(1)
Signaling Power
7(1)
Signal Integrity
8(1)
Other Signaling Conventions
8(1)
1.2.3 Timing and Synchronization
8(1)
Synchronous Timing
8(1)
Pipelined Timing
9(1)
Closed-Loop Timing
9(1)
Clock Distribution
9(1)
Synchronization
10(1)
1.2.4 Power Distribution
10(1)
1.2.5 Noise
10(2)
1.2.6 A Systems View of Circuits
12(1)
1.3 Technology Trends and Digital Systems Engineering
12(10)
1.3.1 Moore's Law
12(4)
1.3.2 Scaling of Chip Parameters
16(1)
1.3.3 Scaling of Wires
17(1)
Scaling of Power Distribution
18(1)
Scaling of On-Chip Communication
18(1)
Scaling of Off-Chip Communication
19(2)
1.3.4 High Levels of Integration Permit New Approaches
21(1)
1.3.5 Digital Systems Problems and Solutions Continue to Change
21(1)
1.4 Organization of this Book
22(1)
1.5 Bibliographic Notes
22(1)
1.6 Exercises
22(3)
2 PACKAGING OF DIGITAL SYSTEMS
25(54)
2.1 A Typical Digital System
27(2)
2.2 Digital Integrated Circuits -- On-Chip Wiring
29(1)
2.3 Integrated Circuit Packages
30(9)
2.3.1 Wire Bonds and Solder Balls
30(2)
2.3.2 Package Types
32(3)
2.3.3 Package Manufacturing Processes
35(1)
2.3.4 Multichip Modules
36(1)
2.3.5 A Typical Package Model
36(1)
Physical Construction
36(1)
Package Electrical Model
37(2)
2.4 Printed Circuit Boards
39(8)
2.4.1 PC Board Construction
40(1)
2.4.2 Electrical Properties
41(1)
2.4.3 Manufacturing Process
42(1)
2.4.4 Vias
42(2)
2.4.5 Dimensional Constraints
44(1)
2.4.6 Mounting Components: Surface-Mount and Through-Hole
44(2)
2.4.7 Sockets
46(1)
2.5 Chassis and Cabinets
47(1)
2.6 Backplanes and Mother Boards
48(1)
2.6.1 Daughter Cards
48(1)
2.6.2 Backplanes
48(1)
2.7 Wire and Cable
49(5)
2.7.1 Wires
49(2)
2.7.2 Signaling Cables
51(1)
Coaxial Cable
51(1)
Ribbon Cable
52(1)
Twisted Pair
53(1)
Flex-Circuit Cable
53(1)
2.7.3 Bus Bars
53(1)
2.8 Connectors
54(8)
2.8.1 PC Board Connectors
55(1)
2.8.2 Interposers
56(1)
2.8.3 Elastomeric Connectors
57(1)
2.8.4 Power Connectors
58(1)
2.8.5 Wire and Cable Connectors
58(1)
Wire Harness Connectors
58(2)
Coaxial Connectors
60(1)
Ribbon-Cable Connectors
60(1)
Methods of Attachment
61(1)
2.9 Optical Communication
62(9)
2.9.1 Optical Transmitters
63(1)
LEDs
63(1)
Laser Diodes
63(1)
2.9.2 Optical Fiber
64(1)
Multimode Fiber
65(1)
Single-Mode Fiber
66(1)
Optical Connectors
66(1)
2.9.3 Optical Receivers
67(1)
2.9.4 Multiplexing
68(1)
Wavelength-Division Multiplexing
68(1)
Time-Division Multiplexing
69(1)
2.9.5 Optical Amplifiers
70(1)
2.9.6 Free-Space Optical Interconnect
70(1)
2.10 Radio Communication
71(6)
2.10.1 A Typical Digital Radio
71(1)
2.10.2 The Power Equation
72(2)
2.10.3 Modulation
74(1)
Amplitude Modulation
74(1)
Phase Modulation (PM)
74(1)
Frequency Modulation
75(1)
Code-Division Multiple Access (CDMA)
75(1)
2.10.4 Multipath
76(1)
2.11 Bibliographic Notes
77(1)
2.12 Exercises
77(2)
3 MODELING AND ANALYSIS OF WIRES
79(69)
3.1 Geometry and Electrical Properties
81(3)
3.1.1 Resistance
81(1)
3.1.2 Capacitance
82(2)
3.1.3 Inductance
84(1)
3.2 Electrical Models of Wires
84(4)
3.2.1 The Ideal Wire
84(1)
3.2.2 The Transmission Line
85(1)
Partial Differential Equation
85(1)
Impedance of an Infinite Line
86(1)
Frequency-Domain Solution
87(1)
Signal Returns
87(1)
Lumped Models of Transmission Lines
88(1)
3.3 Simple Transmission Lines
88(18)
3.3.1 Lumped Wires
88(1)
Lumped Capacitive Loads
88(1)
Lumped Resistive Lines
89(1)
Lumped Inductive Lines
90(1)
Lumped Models of Impedance Discontinuities
90(1)
3.3.2 RC Transmission Lines
90(1)
Step Response of an RC Line
91(1)
Low-Frequency RC Lines
92(1)
3.3.3 Lossless LC Transmission Lines
92(1)
Traveling Waves
92(1)
Impedance
93(1)
Driving LC Transmission Lines
93(2)
Reflections and the Telegrapher's Equation
95(1)
Some Common Terminations
96(1)
Source Termination and Multiple Reflections
97(1)
Arbitrary Termination
97(2)
Standing Waves
99(1)
Summary
100(1)
3.3.4 Lossy LRC Transmission Lines
100(1)
Wave Attenuation
100(1)
DC Attenuation
101(1)
Combined Traveling Wave and Diffusive Response
102(1)
The Skin Effect
103(2)
3.3.5 Dielectric Absorption
105(1)
3.4 Special Transmission Lines
106(7)
3.4.1 Multidrop Buses
106(2)
3.4.2 Balanced Transmission Lines
108(2)
3.4.3 Common- and Differential-Mode Impedance
110(1)
3.4.4 Isolated Lines
111(1)
AC Coupling
112(1)
Optical Isolation
113(1)
3.5 Wire Cost Models
113(4)
3.5.1 Wire Area Costs
114(2)
3.5.2 Terminal Costs
116(1)
3.6 Measurement Techniques
117(9)
3.6.1 Time-Domain Measurements
117(1)
The Time-Domain Reflectometer
117(2)
Rise Time and Resolution
119(1)
Lumped Discontinuities
120(1)
Transmission Measurements
121(1)
Cross Talk Measurements
121(1)
3.6.2 Network Analysis
122(2)
3.6.3 CAD Tools for Characterizing Wires
124(1)
Spreadsheets
124(1)
Two-Dimensional Electromagnetic Field Solvers
124(1)
Signal Integrity Software Packages
125(1)
3D Electromagnetic Field Solvers
126(1)
3.7 Some Experimental Measurements
126(16)
3.7.1 Frequency-Dependent Attenuation in a PC Board Trace
127(1)
DC Resistance and Attenuation Calculations
127(1)
High-Frequency Attenuation Factors
128(3)
3.7.2 Cross Talk in Coupled Lines
131(1)
Coupled Embedded Striplines
131(2)
Coupled Inhomogeneous Lines
133(1)
Coupling Between Lines at Right Angles
134(1)
3.7.3 Inductive and Capacitive Discontinuities
134(4)
3.7.4 Measurement of IC Package Parasitics
138(4)
3.7.5 Measurement Practice
142(1)
3.8 Bibliographic Notes
142(1)
3.9 Exercises
143(5)
4 CIRCUITS
148(73)
4.1 MOS Transistors
149(10)
4.1.1 MOS Device Structure
150(1)
4.1.2 Current-Voltage Characteristics
151(1)
Threshold Voltage
151(1)
Resistive Region
152(1)
Saturation Region
152(1)
p-Channel FETs
153(1)
Channel-Length Modulation
154(1)
Body Effect
155(1)
Velocity Saturation
156(1)
Subthreshold Conduction
156(1)
Typical I-V Curves
157(1)
Enhancement and Depletion Devices
158(1)
4.1.3 Parameters for a Typical 0.35 -um CMOS Process
158(1)
4.2 Parasitic Circuit Elements
159(6)
4.2.1 Parasitic Capacitors
160(1)
Gate Capacitance
160(2)
Source and Drain Diodes
162(1)
4.2.2 Parasitic Resistance
162(1)
4.2.3 A Typical Device
163(1)
4.2.4 SPICE Models
163(2)
4.3 Basic Circuit Forms
165(45)
4.3.1 Switch Networks
166(1)
Pass Gates
166(1)
Logic with Switches
167(1)
Circuits Using Switches
167(1)
Transient Analysis of Switch Networks
168(2)
4.3.2 The Static CMOS Gate
170(1)
Inverter DC Transfer Characteristics
170(2)
Inverter Gain
172(1)
Transient Response
173(3)
Propagation Delay and Nonzero Rise Time
176(1)
The Effect of Input Rise Time on Delay
177(1)
Asymmetrical Sizing
178(1)
Miller-Effect Capacitance
179(1)
Gain-Bandwidth Product
180(1)
The Exponential Horn
181(1)
SPICE Simulations of Gates
182(2)
4.3.3 Dynamic Circuits
184(1)
The Dynamic Latch
184(2)
Precharged Gates
186(1)
Domino Logic
187(2)
Dual-Rail Domino
189(1)
Bootstrap Circuits
190(1)
4.3.4 Source Followers and Cascodes
191(1)
Source Follower
192(2)
Cascode
194(1)
4.3.5 Current Mirrors
195(1)
The Basic Current Mirror
196(1)
The Cascode Current Mirror
197(2)
4.3.6 The Source-Coupled Pair
199(1)
V-I Characteristics of the Source-Coupled Pair
199(1)
Differential Circuit Analysis
200(1)
Differential Loads
201(1)
Mode Coupling
202(1)
FET Resistors
203(1)
A Simple Differential Amplifier
204(3)
4.3.7 Regenerative Circuits and Clocked Amplifiers
207(3)
4.4 Circuit Analysis
210(5)
4.4.1 Qualitative Circuit Analysis
210(1)
Qualitative Analysis of a Differential Amplifier
210(1)
Qualitative Analysis of a Voltage-Controlled Oscillator
211(1)
4.4.2 Power Dissipation
212(1)
Power Dissipation of a Static CMOS Gate
212(1)
Energy-Delay Product of a CMOS Gate
213(1)
AC Versus DC Power
214(1)
Power Dissipation of Source-Coupled FET Logic
215(1)
4.5 Bibliographic Notes
215(1)
4.6 Exercises
216(5)
5 POWER DISTRIBUTION
221(39)
5.1 The Power Supply Network
222(6)
5.1.1 Local Loads and Signal Loads
224(1)
Local Loads
224(1)
Signal Loads
224(1)
5.1.2 Inductive Power Supply Noise
225(3)
5.2 Local Regulation
228(9)
5.2.1 Clamps and Shunt Regulators
228(2)
5.2.2 Series Regulators
230(1)
Linear Regulator
231(2)
Switching Regulator
233(4)
5.3 Logic Loads and On-Chip Power Supply Distribution
237(8)
5.3.1 Logic Current Profile
237(3)
5.3.2 IR Drops
240(2)
5.3.3 Area Bonding
242(1)
5.3.4 Metal Migration
243(1)
5.3.5 On-Chip Bypass Capacitors
243(1)
5.3.6 Symbiotic Bypass Capacitance
244(1)
5.4 Power Supply Isolation
245(2)
5.4.1 Supply-Supply Isolation
245(1)
5.4.2 Signal-Supply Isolation
246(1)
5.5 Bypass Capacitors
247(2)
5.6 Example Power Distribution System
249(7)
5.7 Bibliographic Notes
256(1)
5.8 Exercises
256(4)
6 NOISE IN DIGITAL SYSTEMS
260(44)
6.1 Noise Sources in a Digital System
261(2)
6.2 Power Supply Noise
263(4)
6.2.1 Single Supply Noise
264(2)
6.2.2 Differential Supply Noise
266(1)
6.2.3 Internal and External Supply Noise
267(1)
6.3 Cross Talk
267(13)
6.3.1 Cross Talk to Capacitive Lines
268(1)
Coupling to a Floating Line
268(1)
Coupling to a Driven Line
269(1)
Typical Capacitance Values
270(1)
Capacitive Cross Talk Countermeasures
271(1)
6.3.2 Cross Talk to Transmission Lines
272(1)
Capacitive and Inductive Coupling of Transmission Lines
272(2)
Lumped Inductive Coupling
274(1)
Near- and Far-End Cross Talk
274(2)
Typical Coupling Coefficients
276(1)
Transmission Line Cross Talk Countermeasures
277(1)
6.3.3 Signal Return Cross Talk
278(2)
6.3.4 Power Supply Cross Talk
280(1)
6.4 Intersymbol Interference
280(5)
6.4.1 Impedance Mismatch and Reflections
281(1)
6.4.2 Resonant Transmitter Circuits
282(1)
6.4.3 Inertial Delay and Hidden State
282(3)
6.5 Other Noise Sources
285(7)
6.5.1 Alpha Particles
286(2)
6.5.2 Electromagnetic Interference
288(1)
6.5.3 Process Variation
288(1)
Typical Process Variations
289(1)
Inverter Offset
289(1)
Inverter Compensation
290(1)
Differential Pair Offset
290(1)
6.5.4 Thermal (Johnson) Noise
291(1)
6.5.5 Shot Noise
291(1)
6.5.6 Flicker or 1/f Noise
292(1)
6.6 Managing Noise
292(6)
6.6.1 Bounded Noise and Noise Budgets
292(1)
Proportional Noise Sources
293(1)
Fixed Noise Sources
294(1)
Overall Noise Budgets
295(1)
6.6.2 Gaussian Noise and Bit Error Rates
296(2)
6.7 Bibliographic Notes
298(1)
6.8 Exercises
298(6)
7 SIGNALING CONVENTIONS
304(52)
7.1 A Comparison of Two Transmission Systems
306(7)
7.1.1 Signal Energy and System Power
308(1)
7.1.2 Noise Immunity Versus Noise Margin
308(3)
7.1.3 Delay
311(1)
7.1.4 Discussion
312(1)
7.2 Considerations in Transmission System Design
313(1)
7.3 Signaling Modes for Transmission Lines
314(17)
7.3.1 Transmitter Signaling Methods
315(1)
Current-Mode Transmission
315(1)
Voltage-Mode Transmission
316(1)
Transmitter Signal-Return Cross Talk
316(2)
Bipolar Versus Unipolar Signaling
318(1)
Transmitter-Generated References
319(1)
7.3.2 Receiver Signal Detection
320(1)
Generating the Receiver Reference
320(1)
Receiver Return Cross Talk
321(1)
Power Supply Noise
322(1)
7.3.3 Source Termination
323(2)
Noise Considerations
325(1)
Power Dissipation
325(1)
Current-Mode Source Termination
326(1)
7.3.4 Underterminated Drivers
327(1)
7.3.5 Differential Signaling
328(2)
Symmetric Transmission Lines
330(1)
7.4 Signaling Over Lumped Transmission Media
331(13)
7.4.1 Signaling Over a Capacitive Transmission Medium
331(1)
Voltage-Mode Signaling
332(1)
Current-Mode Signaling
333(1)
Resistive Voltage Divider
333(1)
Pulsed Signaling
334(1)
Return-to-Zero (Precharged) Pulsed Signaling
335(1)
Band-Limited Pulsed Signaling
336(1)
References
336(1)
7.4.2 Signaling over Lumped LRC Interconnect
337(2)
Rise-Time Control
339(3)
Adding Parallel Termination
342(1)
Reducing Power Supply Noise
343(1)
7.5 Signal Encoding
344(8)
7.5.1 Number of Signal Levels
345(2)
7.5.2 Signal Magnitude
347(1)
Hysteresis
347(1)
7.5.3 Signal Transfer Function
348(1)
7.5.4 Error Correcting Codes
349(1)
7.5.5 Pulsed Signaling
350(1)
7.5.6 Signal Level and Delay
351(1)
7.6 Bibliographic Notes
352(1)
7.7 Exercises
353(3)
8 ADVANCED SIGNALING TECHNIQUES
356(38)
8.1 Signaling over RC Interconnect
357(5)
8.1.1 Circuit Model
357(2)
8.1.2 Repeaters
359(1)
8.1.3 Increasing Wire Width and Spacing
360(1)
8.1.4 Overdrive of Low-Swing RC Lines
361(1)
8.2 Driving Lossy LC Lines
362(4)
8.2.1 The Lone Pulse
363(1)
8.2.2 Equalization of LRC Lines
364(2)
8.3 Simultaneous Bidirectional Signaling
366(6)
8.3.1 Current-Mode Bidirectional Signaling
367(1)
8.3.2 Bidirectional Signaling Waveforms
368(1)
8.3.3 Differential Simultaneous Bidirectional Signaling
368(2)
8.3.4 Voltage-Mode Simultaneous Bidirectional Signaling
370(1)
8.3.5 Reverse-Channel Cross Talk
371(1)
8.4 AC and N of M Balanced Signaling
372(9)
8.4.1 Terminology
372(1)
DC Offset
372(1)
Run Length
373(1)
Disparity or Digital-Sum Variation (DSV)
374(1)
8.4.2 Codes for DC-Balancing Signals
374(1)
Nonoverlapping Block Codes
374(1)
Running-Disparity Encoding
375(2)
Framing
377(1)
Burst-Error Length
377(1)
The 8b/10b Code
378(1)
DC Restoration
379(1)
8.4.3 Spatial N of M Balanced Signaling
379(1)
Coding Efficiency
380(1)
Systematic Encoding
380(1)
8.5 Examples
381(11)
8.5.1 Logic Signaling
382(1)
8.5.2 SRAM Bit Lines
383(2)
8.5.3 Signaling Over Long On-Chip Wires
385(2)
8.5.4 Signaling Chip-to-Chip on a Board
387(2)
8.5.5 Signaling across a Cable
389(3)
8.6 Bibliographic Notes
392(1)
8.7 Exercises
392(2)
9 TIMING CONVENTIONS
394(68)
9.1 A Comparison of Two Timing Conventions
396(4)
9.1.1 Skew and Jitter Analysis
398(1)
9.1.2 Allowable Clock Rates
399(1)
9.1.3 Discussion
400(1)
9.2 Considerations in Timing Design
400(1)
9.3 Timing Fundamentals
401(10)
9.3.1 Timing Nomenclature
401(1)
Delay and Transition Times
401(1)
Periodic Signals
401(2)
Maximum Absolute Value, Peak-to-Peak, and RMS
403(1)
9.3.2 Timing Properties of Delay Elements
403(2)
9.3.3 Timing Properties of Combinational Logic
405(1)
9.3.4 Timing Properties of Clocked Storage Elements
406(1)
Edge-Triggered Flip-Flop
406(1)
Level-Sensitive Latch
407(1)
Double-Edge-Triggered Flip-Flop
408(1)
9.3.5 The Eye Diagram
409(2)
9.4 Encoding Timing: Signals and Events
411(4)
9.4.1 Encoding Aperiodic Events
411(1)
Dual-Rail Signaling
411(1)
Return-to-Zero (RZ)/Nonreturn-to-Zero (NRZ) Signaling
412(1)
Clocked Signaling and Bundling
412(1)
Ternary Signaling
413(1)
9.4.2 Encoding Periodic Signals
413(1)
Required Transition Frequency
414(1)
Bit Stuffing
414(1)
Phase-Encoding
414(1)
9.5 Open-Loop Synchronous Timing
415(13)
9.5.1 Global Clock, Edge-Triggered Timing
416(1)
Minimum Delay Constraint
416(1)
Maximum Delay Constraint
417(1)
9.5.2 Level-Sensitive Clocking
418(1)
Basic Two-Phase Clocking
418(1)
Borrowing Time
419(1)
Effect of Skew
420(1)
Qualified Clocks
420(1)
Signal Labeling for Two-Phase Clocking
421(1)
Single-Phase or Zero Nonoverlap Clocking
422(1)
9.5.3 Pipeline Timing
423(2)
Optimum Clock Delay
425(1)
Level-Sensitive Pipeline Timing
426(1)
Pipelines With Feedback
427(1)
9.6 Closed-Loop Timing
428(21)
9.6.1 A Simple Timing Loop
428(1)
Residual Error
429(1)
Loop Dynamics
429(1)
9.6.2 Phase Comparators
430(1)
Flip-Flop Phase Comparator
431(2)
Exclusive-OR (XOR) Phase Comparator
433(1)
Sequential Phase and Frequency Comparator
434(2)
9.6.3 Variable Delay Line
436(1)
9.6.4 Bundled Closed-Loop Timing
436(2)
Canceled and Uncanceled Sources of Timing Uncertainty
438(1)
Integrating Receivers
438(1)
9.6.5 Per-Line Closed-Loop Timing
439(2)
9.6.6 Phase-Locked Loops
441(1)
Voltage-Controlled Oscillators
442(1)
Frequency Comparator
443(1)
Loop Dynamics and Loop Filter
444(2)
Reducing Jitter with a Phase-Locked Loop
446(1)
9.6.7 Oversampling Clock Recovery
447(2)
9.7 Clock Distribution
449(9)
9.7.1 Off-Chip Clock Distribution
449(1)
Clock Distribution Trees
450(1)
Phase-Locked Clock Distribution Networks
451(1)
Salphasic Clock Distribution
452(1)
Round-Trip Distribution
453(1)
9.7.2 On-Chip Clock Distribution
454(1)
On-Chip Clock Trees
454(2)
Mesh Distribution
456(1)
Jitter in On-Chip Clock Distribution
457(1)
9.8 Bibliographic Notes
458(1)
9.9 Exercises
458(4)
10 SYNCHRONIZATION
462(52)
10.1 A Comparison of Three Synchronization Strategies
463(2)
10.2 Synchronization Fundamentals
465(10)
10.2.1 Uses of Synchronization
466(1)
Arbitration of Asynchronous Signals
466(1)
Sampling Asynchronous Signals
466(1)
Crossing Clock Domains
467(1)
10.2.2 Synchronization Failure and Metastability
468(1)
Synchronizer Dynamics and Synchronization Time
468(1)
Metastability
469(1)
Probability of Synchronization Failure
469(1)
Example Synchronizer Calculation
470(1)
Completion Detection
470(1)
Common Synchronizer Mistakes
471(1)
10.2.3 Clock Domains
472(1)
Independent Clock Rates
473(1)
Simplified Clock Distribution
473(1)
Pipelined Signal Timing Eliminates Cable Delay Constraints
473(1)
Aperiodic Clocks
473(1)
10.2.4 Classification of Signal-Clock Synchronization
473(2)
10.3 Synchronizer Design
475(11)
10.3.1 Mesochronous Synchronizers
475(1)
Delay-Line Synchronizer
475(1)
Two-Register Synchronizer
476(1)
FIFO Synchronizer
477(3)
Brute-Force Synchronization
480(1)
10.3.2 Plesiochronous Synchronizers
480(1)
A Plesiochronous FIFO Synchronizer
480(1)
Data Rate Mismatch
481(1)
Detecting Phase Slip
482(1)
Null Symbols and Flow Control
483(1)
10.3.3 Periodic Asynchronous Synchronizers
483(1)
Clock Predictor Circuit
484(1)
Periodic Synchronizer
484(1)
10.3.4 General Purpose Asynchronous Synchronizers
485(1)
Waiting Synchronizer
485(1)
Asynchronous FIFO Synchronizer
485(1)
10.4 Asynchronous Design
486(24)
10.4.1 Stoppable Clocks
487(2)
10.4.2 Asynchronous Signaling Protocols
489(1)
Four-Phase Asynchronous Signaling
489(1)
Two-Phase Asynchronous Signaling
489(1)
The Weak Conditions
490(2)
10.4.3 Asynchronous Module Design Methods
492(1)
State Diagrams
492(2)
Concurrency and Choice
494(1)
Trajectory Maps for Designing Asynchronous Sequential Logic
495(2)
Set-Reset Excitation Equations
497(1)
Arbitration and Circuits with Choice
498(2)
Delay-Insensitive versus Matched-Delay Modules
500(2)
10.4.4 Composition of Asynchronous Circuits
502(1)
Asynchronous Combinational Blocks
502(1)
Align Blocks and Self-Timed Pipelines
503(5)
Cyclic Asynchronous Circuits
508(2)
10.5 Bibliographic Notes
510(1)
10.6 Exercises
511(3)
11 SIGNALING CIRCUITS
514(59)
11.1 Terminations
515(7)
11.1.1 On-Chip Versus Off-Chip Termination
515(1)
11.1.2 FET Terminations
516(1)
11.1.3 Adjustable Terminators
517(1)
Digital Versus Analog Adjustment
518(1)
Binary Versus Thermometer Digital Adjustment Codes
519(1)
11.1.4 Automatic Terminator Adjustment
519(1)
Automated Adjustment Controllers
520(1)
Thermometer-Coded Controllers
521(1)
Self-Series Termination Control
521(1)
11.2 Transmitter Circuits
522(18)
11.2.1 Voltage-Mode Driver
523(1)
Break-Before-Make Action
524(1)
Pulse-Generating Driver
525(1)
Tristate Driver
525(1)
Open-Drain Outputs
526(2)
11.2.2 Self-Series-Terminating Drivers
528(1)
11.2.3 Current-Mode Drivers
529(1)
Saturated FET Driver
529(1)
Current-Mirror Drivers
530(1)
Differential Current-Steering Driver
530(2)
Bipolar Current-Mode Drivers
532(1)
11.2.4 Rise-Time Control
533(1)
Segmented Current Driver
533(1)
The Problem with RC Rise-Time Control
533(1)
Segmented Voltage Driver
534(1)
Segmented Self-Series Terminated Driver
535(1)
11.2.5 Drivers for Lumped Loads
536(1)
On-Chip Drivers for Capacitive Loads
536(1)
Off-Chip Drivers for LRC Loads
537(1)
11.2.6 Multiplexing Transmitters
537(3)
11.3 Receiver Circuits
540(8)
11.3.1 Receivers Using Static Amplifiers
542(1)
The Inverter As a Receiver
542(1)
Source-Coupled FET Receivers
543(1)
11.3.2 Receivers Using Clocked Differential Amplifiers
544(1)
11.3.3 Integrating Amplifiers
545(1)
An Integrating Amplifier
545(1)
Receiver Impulse Response
545(1)
A Matched-Filter Receive Amplifier
546(1)
11.3.4 Demultiplexing Receivers
547(1)
11.4 Electrostatic Discharge (ESD) Protection
548(11)
11.4.1 ESD Failure Mechanisms
550(1)
Field-Induced Failures
550(1)
Thermally Induced Failures
551(1)
11.4.2 ESD Protection Devices
552(1)
Primary Shunt
552(3)
Series Resistor
555(1)
Secondary Shunt
556(1)
Protecting Output Drivers
556(1)
Guard Rings
557(1)
Wiring and Contacting
558(1)
11.5 An Example Signaling System
559(12)
11.5.1 Transmitter
559(1)
Multiphase Clock Generator
559(1)
Output Driver
560(1)
Bias Generator
561(1)
Predriver
562(1)
Latches and Pass-Gate Clocking Network
563(1)
Package Model
563(1)
Transmission Line Model
564(1)
Simulation Results for Package and Transmission-Line Models
564(1)
Termination Schemes
565(1)
Effectiveness of Slew-Rate Control
566(1)
Noise Modeling
566(1)
11.5.2 Receiver
567(1)
Phase Shifter and Multiphase Clock Generator
568(1)
Samplers
569(1)
Retiming Latches
569(1)
Clock Adjuster
569(2)
11.6 Bibliographic Notes
571(1)
11.7 Exercises
571(2)
12 TIMING CIRCUITS
573(80)
12.1 Latches and Flip-Flops
574(15)
12.1.1 Level-Sensitive Latches
574(1)
Dynamic Latches
574(2)
CMOS Static Storage Element
576(1)
CMOS Static Latches
577(2)
12.1.2 Edge-Triggered Flip-Flops
579(1)
Auxiliary Control Inputs
580(1)
True Single-Phase-Clocked (TSPC) Flip-Flops
581(1)
Differential Edge-Triggered Flip-Flop
582(1)
Double-Edge-Triggered Flip-Flops
582(1)
12.1.3 Failure Mechanisms in Flip-Flops and Latches
583(1)
Race-Through
583(1)
Dynamic Node Discharge
584(2)
Power Supply Noise
586(1)
Clock Slope
586(2)
Charge Sharing
588(1)
12.2 Delay Line Circuits
589(19)
12.2.1 Inverter Delay Lines
589(2)
Delay Adjustment Range
591(1)
Power-Supply Rejection in Inverter Delay Elements
592(1)
Inverters with Regulated Supply Voltage
593(1)
12.2.2 Differential Delay Elements
593(1)
Adjustable PFET Resistor
594(1)
Replica-Biased Delay Line
595(1)
Adjustment Range for Replica-Bias Delay Lines
595(1)
Static Supply Sensitivity for the Replica-Biased Delay Stage
596(1)
Dynamic Supply Sensitivity
597(1)
12.2.3 Circuit and Layout Details
598(1)
Replica Control Loop Stability
598(2)
Power Routing and Bypassing
600(1)
Matching and Balancing
601(1)
Substrate Noise
602(1)
12.2.4 Other Differential Timing Components
603(1)
Small-Swing to Full-Swing Buffers
603(1)
Interpolators
604(2)
Duty-Cycle Correctors
606(1)
Clock Input Conditioning
607(1)
12.3 Voltage-Controlled Oscillators
608(7)
12.3.1 First-Order Oscillators
608(1)
Array Oscillators
609(1)
12.3.2 Second-Order Oscillators
610(1)
Crystal Oscillators
610(3)
Frequency Multiplication
613(1)
Lumped-Element Oscillators
613(2)
12.4 Phase Comparators
615(5)
12.4.1 XOR Comparator
615(2)
12.4.2 Edge-Triggered Flip-Flop Phase Detector
617(1)
12.4.3 Sequential Phase Detectors
617(3)
12.5 Loop Filters
620(15)
12.5.1 RC Loop Filters
621(3)
12.5.2 Charge Pump Filters
624(2)
Charge Pump Control Voltage Ripple
626(1)
Self-Biased Loop Filters
627(2)
12.5.3 Delay-Locked Loop Filters
629(1)
Self-Biased DLL Loop Filter
630(1)
Switched-Capacitor Loop Filters
630(1)
Loop Initialization
631(1)
"Turbo" Mode
632(1)
"Bang-Bang" Controllers
633(1)
Digital Loop Controllers
633(2)
12.6 Clock Aligners
635(5)
12.6.1 PLL Versus DLL Implementations
635(1)
12.6.2 Simple DLL-Based Aligners
636(2)
12.6.3 Phase-Based Aligners
638(1)
12.6.4 A Hybrid Phase/Delay-Based Clock Aligner
639(1)
12.7 Bibliographic Notes
640(1)
12.8 Problems
641(12)
Index 653

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