Cryptographic Hardware and Embedded Systems - CHES 2010: 12th International Workshop, Santa Barbara, USA, August 17-20, 2010, Proceedings

by Mangard, Stefan; Standaert, Francois-xavier

ISBN13: 9783642150302

ISBN10: 3642150306

Format: Paperback

Pub. Date: 2010-11-05

Publisher(s): Springer-Verlag New York Inc

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Summary

This book constitutes the refereed proceedings of the 12th International Workshop on Cryptographic Hardware and Embedded Systems, CHES 2010, held in Santa Barbara, USA during August 17-20, 2010.This year it was co-located with the 30th International Cryptology Conference (CRYPTO).The book contains 2 invited talks and 30 revised full papers which were carefully reviewed and selected from from 108 submissions. The papers are organized in topical sections on low cost cryptography, efficient implementation, side-channel attacks and countermeasures, tamper resistance, hardware trojans, PUFs and RNGs.

Low Cost Cryptography
QUARK: A Lightweight Hash	p. 1
PRINTcipher: A Block Cipher for IC-Printing	p. 16
Sponge-Based Pseudo-Random Number Generators	p. 33
Efficient Implementations I
A High Speed Coprocessor for Elliptic Curve Scalar Multiplications over &$$$;	p. 48
Co-Z Addition Formulæ and Binary Ladders on Elliptic Curves	p. 65
Efficient Techniques for High-Speed Elliptic Curve Cryptography	p. 80
Side-Channel Attacks and Countermeasures I
Analysis and Improvement of the Random Delay Countermeasure of CHES 2009	p. 95
New Results on Instruction Cache Attacks	p. 110
Correlation-Enhanced Power Analysis Collision Attack	p. 125
Side-Channel Analysis of Six SHA-3 Candidates	p. 140
Tamper Resistance and Hardware Trojans
Flash Memory 'Bumping' Attacks	p. 158
Self-referencing: A Scalable Side-Channel Approach for Hardware Trojan Detection	p. 173
When Failure Analysis Meets Side-Channel Attacks	p. 188
Efficient Implementations II
Fast Exhaustive Search for Polynomial Systems in &$$$;	p. 203
256 Bit Standardized Crypto for 650 GE - GOST Revisited	p. 219
Mixed Bases for Efficient Inversion in &$$$; and Conversion Matrices of SubBytes of AES	p. 234
SHA-3
Developing a Hardware Evaluation Method for SHA-3 Candidates	p. 248
Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs	p. 264
Performance Analysis of the SHA-3 Candidates on Exotic Multi-core Architectures	p. 279
XBX: eXternal Benchmarking eXtension for the SUPERCOP Crypto Benchmarking Framework	p. 294
Fault Attacks and Countermeasures
Public Key Perturbation of Randomized RSA Implementations	p. 306
Fault Sensitivity Analysis	p. 320
PUFs and RNGs
An Alternative to Error Correction for SRAM-Like PUFs	p. 335
New High Entropy Element for FPGA Based True Random Number Generators	p. 351
The Glitch PUF: A New Delay-PUF Architecture Exploiting Glitch Shapes	p. 366
New Designs
Garbled Circuits for Leakage-Resilience: Hardware Implementation and Evaluation of One-Time Programs	p. 383
ARMADILLO: A Multi-purpose Cryptographic Primitive Dedicated to Hardware	p. 398
Side-Channel Attacks and Countermeasures II
Provably Secure Higher-Order Masking of AES	p. 413
Algebraic Side-Channel Analysis in the Presence of Errors	p. 428
Coordinate Blinding over Large Prime Fields	p. 443
Author Index	p. 457
Table of Contents provided by Ingram. All Rights Reserved.