Advanced Digital Design with the Verilog HDL
by Ciletti, Michael D.Edition: 2nd
Format: Hardcover
Pub. Date: 2010-01-21
Publisher(s): Pearson
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Summary
This first edtion book covers the key design problems of modeling, architectural tradeoffs, functional verification, timing analysis, test generation, fault simulation, design for testablility, logic synthesis, and post-synthesis verification. The author's focus is on developing, verifying, and synthesizing designs of digital circuits rather than on the Verilog language.Some of the topics covered in this book include Digital Design Methodology, Combinational Logic, Sequential Logic Design, Logic Design with Verilog, and Programmable Logic and Storage Devices.For professional engineers interested in learning Verilog by example, in the context of its use in the design flow of modern integrated circuits.
Author Biography
Michael Ciletti is Professor Emeritus in the Department of Electrical and Computer Engineering at the University of Colorado, Colorado Springs. His areas of interest include Modeling, synthesis and verification of digital systems with hardware description languages, system-level design languages, and embedded systems with FPGAs. He is the author of Advanced Digital Design with the Verilog HDL and the co-author of Digital Design, 4e.
Table of Contents
| Introduction to Digital Design Methodology | |
| Design Methodology - An Introduction | |
| IC Technology Options | |
| Overview | |
| Review of Combinational Logic Design | |
| Combinational Logic and Boolean Algebra | |
| Theorems for Boolean Algebraic Minimization | |
| Representation of Combinational Logic | |
| Simplification of Boolean Expressions | |
| Glitches and Hazards | |
| Building Blocks for Logic Design | |
| Fundamentals of Sequential Logic Design | |
| Storage Elements | |
| Flip-Flops | |
| Busses and Three-State Devices | |
| Design of Sequential Machines | |
| State Transition Graphs | |
| Design Example: BCD to Excess-3 Code Converter | |
| Serial Line Code Converter for Data Transmission | |
| State Reduction and Equivalent States | |
| Introduction to Logic Design with Verilog | |
| Structural Models of Combinational Logic | |
| Logic Simulation, Design Verification, and Testbenches | |
| Propagation Delay | |
| Truth Table Models of Combinational and Sequential Logic with Verilog | |
| Logic Design with Behavioral Models of Combinational and Sequential Logic | |
| Behavioral Modeling | |
| A Brief Look at Data Types for Behavioral Modeling | |
| Boolean Equation-Based Behavioral Models of Combinational Logic | |
| Propagation Delay and Continuous Assignments | |
| Latches and Level-Sensitive Circuits in Verilog | |
| Cyclic Behavioral Models of Flip-Flops and Latches | |
| Cyclic Behavior and Edge Detection | |
| A Comparison of Styles for Behavioral Modeling | |
| Behavioral Models of Multiplexers, Encoders, and Decoders | |
| Dataflow Models of a Linear Feedback Shift Register | |
| Modeling Digital Machines with Repetitive Algorithms | |
| Machines with Multi-Cycle Operations | |
| Design Documentation with Functions and Tasks: Legacy or Lunacy? | |
| Algorithmic State Machine Charts for Behavioral Modeling | |
| ASMD Charts | |
| Behavioral Models of Counters, Shift Registers, and Register Files | |
| Switch Debounce, Metastability, and Synchronizers for Asynchronous Signals | |
| Design Example: Keypad Scanner and Encoder | |
| Synthesis of Combinational and Sequential Logic | |
| Introduction to Synthesis | |
| Synthesis of Combinational Logic | |
| Synthesis of Sequential Logic with Latches | |
| Synthesis of Three-State Devices and Bus Interfaces | |
| Synthesis of Sequential Logic with Flip-Flops | |
| Synthesis of Explicit State Machines | |
| Registered Logic | |
| State Encoding | |
| Synthesis of Implicit State Machines, Registers, and Counters | |
| Resets | |
| Synthesis of Gated Clocks and Clock Enables | |
| Anticipating the Results of Synthesis | |
| Synthesis of Loops | |
| Design Traps to Avoid | |
| Divide and Conquer: Partitioning a Design | |
| Design and Synthesis of Datapath Controllers | |
| Partitioned Sequential Machines | |
| Design Example: Binary Counter | |
| Design and Synthesis of a Risc Stored Program Machine | |
| Design Example: Uart | |
| Programmable Logic and Storage Devices | |
| Programmable Logic Devices | |
| Storage Devices | |
| Programmable Logic Array (PLA) | |
| Programmable Array Logic (PALTM) | |
| Programmability of PLDs | |
| Complex PLDs (CPLDs) | |
| Altera Max 7000 CPLD | |
| XILinx XC9500 CPLDs | |
| Field Programmable Gate Arrays | |
| Altera Flex 8000 FPGAs | |
| Altera Flex 10 FPGAs | |
| Altera Apex FPGAs | |
| Altera Chip Programmability | |
| XILinx XC4000 Series FPGA | |
| XILinx Spartan XL FPGAs | |
| XILinx Spartan II FPGAs | |
| XILinx Virtex FPGAs | |
| Embeddable and Programmable IP Cores for a System on a Chip (SOC) | |
| Verilog-Based | |
| Table of Contents provided by Publisher. All Rights Reserved. |
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